本文介绍在Canence ORCAD capture中的新增功以及加强功能,以及对PCBs的修正问题
设定零件序号范围
Capture15.7可轻松快速地指定项目中电路图纸或阶层式电路方块零件的序号范围。
平坦式电路图设计： 可设定主图上每页图纸上零件的特殊零件序号范围。
阶层式电路设计： 可设定主图上每个阶层式电路方块下零件的特殊零件序号范围。
当我们勾选 Annotate 功能选项中的 Refdes control required 选项， scope 选项会自动选择电路图设计为 Schematic Pages 或 Hierarchical Block s。如下图示：
Schematic Pages ：
Hierarchical Blocks depending：
当我们执行 Annotate 功能选项中的 Refdes control required 选项，若有错误的操作时，便会出现警告讯息提示。如下所示：若设定的零件序号范围比实际图纸零件数少
出现此提示讯息：
Capture 的零件库中包含PSpice ground(0)
PSpice ground (0)符号为PSpice 模拟电路仿真时必须一定存在的参考接地点，现在Capture 15.7将PSpice ground(0)符号加在 Capture的CAPSYM.OLB零件库中。
另外，在开启新的 PSpice 项目时，多了 AnalogGNDSymbol.opj 项目选项，当我们开启此项目，图纸中已包含 PSpice ground(0) 符号，让设计电路时更加方便。
快速切换license feature
在Capture15.7中，当我们想切换产品使用时可不用关闭Capture软件便能进行切换。请在项目管理窗口中选择File中的change product选项或同时按键盘上的ALT，F，C键也可达相同目的（若有开启图纸项目，此选项便不会出现，请关闭图纸项目方可进行切换产品的功能）。
跳出此产品选择盒，便能直接选择要切换的产品，若勾选Use as default选项，下次开启软件时就不会再出现此产品选择盒，会直接进入您设定default的产品中。如果下次开启软件时想让此产品选择盒再次出现，将Use as default选项取消即可。
电路图图纸与属性编辑窗口支持鼠标滚轮
在 Capture15.7 中，电路图图纸与属性编辑窗口里，可直接利用鼠标滚轮做垂直上下移动及水平左右移动使得更方便能观看图纸与属性。
将鼠标滚轮按住并左右或上下移动，也可达到在电路图图纸与属性编辑窗口内水平或垂直移动功能
当按住键盘上 CTRL 键及将鼠标滚轮上滚，可达 zoom out 功能；反之，按住键盘上 CTRL 键及将鼠标滚轮下滚，可达 zoom in 功能。
若按住键盘上 SHIFT 键鼠标滚轮上下滚动，亦可达窗口内水平移动。
对象搬移联机行为选项
在 Capture 15.7 中，当我们将对象搬移到另一区域时，若会改变对象的联机关系时， 则会出现 
标志 提示对象的联机关系将被改变及 ? 标志提示会造成电器线联机关系被短路的位置。
在 Miscellaneous 窗口中的 Wire Drag 选项，可设定是否允许对象搬移时造成电器线联机关系更改。
除了在 Miscellaneous 窗口中可设定外也可直接在图纸工具列做此设定。
反之，在 Miscellaneous 窗口中不勾选 Wire Drag 选项或图纸工具列中的 UI 不选择此功能时，则电路图做搬移对象时造成电器线联机间原本不相接的变成短路，依然会显示出标示提醒我们联机关系会不同，并且不允许对象被搬移到此。
支持signal flow属性单位值
在 Capture 15.7 中，支持 PCB Editor 中 PROPAGATION_DELAY 和 RELATIVE_PROPAGATION_DELAY 属性单位，包括以下单位：
_ Micron ( um )
_ Millimeter ( mm )
_ Centimeter ( cm )
_ Inches ( in )
自订netlist 输出格式
15.7 版在转出 Netlist 的 other 页面下多加了 config 文件的控制选项。您可利用此 config 档来控制转出各种格式的 netlist 之前的萃取联机档 .ONL 当中的属性项目定义，详细的设定请参阅辅助说明 。
快速进入阶层式电路方块之下层电路
在 Capture 15.7 中，欲到阶层式电路方块底层电路，可直接快点两下此阶层式电路方块便可到其底层电路
多媒体动画教学
我们可利用 OrCAD Capture Help 中点选 Documentation 选项，进入网页后选择 Learning Aid s， 其中包括了 Captur 功能的操作动画，更还有在 Capture 15.7 中才有的新功能 Controlled annotation of part s也在其中，因此可透过 动画说明更加了解操作方式。
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一些重要的 PCRs 如下列表
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561740
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Double the zoom level to 1008% in Library/Part editor. This will help in designing graphic objects.
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650279
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PXL-Lite error message does not contain any explanation.
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702252
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Enhance the Update Cache option to preserve the Reference Designator and Value properties.
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706629
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Design Rules Check does not report stray nets connected to a BUS.
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755278
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Export property should have a report PIN_NUMBER and netname.
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761532
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Unable to edit a part once it has been split.
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761812
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Pin Shape/Type option should be in Split Part Section Input Spreadsheet.
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724163
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Relative propagation delay constraints assigned to same pinpairs on different nets.
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791974
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Capture crashes when importing from EDIF and also the PCB Footprint Property is deleted.
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791123
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Unable to open design in Capture. The following error message appears “Exception while opening OLE storage”.
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788801
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Unable to recover corrupt design. July 2006 26 Product Version 15.7
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787802
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Capture CIS 10.3 crashes when using the Cleanup Cache command from the Design Cache pop-up menu.
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780846
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The error message displayed during generating a Layout netlist has incorrect text.
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777753
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Editing properties is slow for large designs in Capture.
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766139
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While archiving a PSpice project, the simulation output files are archived automatically irrespective of whether the Output files check box is checked or not in the Archive Project dialog box.
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762802
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The Split Part Section Input Spreadsheet should allow entering Pin Swapping information.
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761900
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Unable to update the pin names in the Split Part, after the pin list has been updated.
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756925
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If a part is pasted on a schematic page with the Auto reference placed part check box checked in the Miscellaneous dialog box, the part references are not preserved.
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751138
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Pin name not being imported correctly from EDIF to Capture.
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750570
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Exporting a Capture design to EDIF and then importing the design from EDIF to Capture results in loss of graphics.
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748382
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The text in the design has squares like "[ ]" replacing spaces.
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747491
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Capture crashes when using a specific Value property.
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746894
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Avoid changing of implementation path for design reuse block.
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742249
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If a design is imported with EDIF, the Title Blocks cannot be printed.
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739970
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Any changes made to text objects on a schematic page does not get saved by clicking the Save All button.
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738529
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Preserve Properties option in the Replace Cache pop-up menu should not move properties.
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728565
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When creating an Allegro netlist, the Output Board File is set to allegro\cisflow.brd in the Create Netlist dialog box.
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728533
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The Capture CIS splash screen should not obscure working with other applications.
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724120
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When the ads_sdlog variable is set in Allegro, it breaks backannotation in Capture.
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722362
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When creating a Allegro netlist, if the OK button is clicked in the error message box, Capture goes into an endless loop.
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695825
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Multiple Bias voltages on a single net slows down Capture refresh.
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684892
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Reference designators not shown correctly, if the package is greater than 10.
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680915
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During the cut and paste operation, the annotation of parts does not work properly.
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663622
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Problem with incremental annotation with heterogeneous parts in Capture.
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659634
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When running a design through the Allegro netlister some properties from one net overwrite the properties of another.
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658823
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No error message appears when the Allegro netlist fails.
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658049
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Capture-to-Allegro Viewer Plus cross probing issue.
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653515
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In Capture 10.0, select all components and then going to property editor window takes about 45 seconds for each operation, whereas in Capture 9.2.3 it just comes up.
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650289
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Parts with color body obscure pin names in Capture 10.0.
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574235
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Capture symbols over 10 parts per packages appearing incorrectly in the cross reference report.
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475945
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Design file size increases upon rearranging of nets.
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804439
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Relative Propagation Delay not getting back annotated.
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