返回PCB资源网首页 注册 | 登陆
PCB资源网-最丰富的PCB|EDA|SMT资源网(线路板起专业网站)
PCB打样 PCB样板制作

Cadence软件应用问题归纳和摘抄

来源:中国PCB技术网 作者:alex1202 发布时间:2008-04-12 发表评论

这是在cadence网站的FAE回答的一些有关allegro和specctra的问题的归纳和摘抄

Answer : Make a backup copy of your .brd database.
* Adjust the names and ordering of your stack-up to your intended preference, plus one more layer as a temporary place holder: don't worry, just yet, about the physical etch position. (Caveat: you may wreak havoc on your extended physical rules if extensively defined but you should revisit them anyway since you are changing the PCB structure.)
* Create a clip file (sub-drawing) containing all the etch features you would like to retain. File --> export --> sub-drawing, select the features you want with temp group in conjunction with FIND filter and/or dragging a rectangle to box an area, pick a reference origin, (0,0) is an easy choice. Name the sub-drawing file and save it.
* Open the saved .clp file with an "ASCII" text editor and perform a systematic search and replace of your was/is layer names. Draw a layer mapping diagram to make it easy to follow and check-off each step. Step 1 is to rename the etch features on one layer to the "empty" place holder layer. Complete the search and replace for all the layers, each time renaming the next layer to the one previously moved. The last step is to rename the place-holder layer to the last move-to layer. Save the .clp file (Text editor) with the layer mapping of the newly defined etch features.
* Go back to Allegro board database and remove the unwanted (obsolete etch).
* Then import the (text modified) .clp sub-drawing file and you should now have the etch features on the layers the way you want.
Caveat: (You will now have a Clip attribute on this etch. AND hopefully you will not be breaking any of the connections by the re-mapping to a layer that has an incorrect or now obsolete via structure from what you had before. It depends on your design but think about this in advance of doing this task. If this is a significant issue, there are workarounds for this as well.

Note: It may take you more than one attempt to accomplish this task flawlessly. But if you follow a systematic flow you will improve your success rate dramatically. If you get it right on first attempt, congratulations you have done a fine job.

2. Route diff pairs without via
Question: I am new to specctra and allegro. I am currently trying to auto-route a board that is mostly diff pairs with lenght requirements. How do I turn off vias so that the dif pairs stay on the one layer? Thanks,....Michael
Answer 1: If you want to retain diff pairs on a specified layer,you should not turn off the vias,you can use net/class layer rule to keep a diff pairs on a desire layer.
Although diff pairs should be at least two vias for fanout (from Top/Botton layer to an internal layer),except 2 layer boards.
Try using Class layer rule.(diff pairs are defined as a class).
Also you can use restricted layer rule to allow diff pairs to route on other layer if autorouter can not route it on specified layer.(you can set restricted length such as 150 mil,...)
Regards,
Saeed
Answer 2 : After fanning out the diffpairs (and protect this particular fanout), then the next question is: are these 2 pin nets, or more pins?
For two pin nets, turn off vias for this class. Define the class (I'll call it diffs).
Then, no vias allowed:
rule class diffs (limit_via 0)
It'll just route on one layer.
If there's more than 2 pins per net, you'll need to define a specific layer for each diffpair with use_layer. In version 15, you'll be able to use the new layer set capability. You can then tell SPECCTRA to route a diffpair on a single layer out of many allowable layers (use layer 2 3 4 5 but only use one of them).

3. Diff pair seperating in the middle of the run
Question: I am routing diff pairs with matched lengths. The problem is that one of the nets in the pair will seperate from the other for a short distance in order to adjust to the correct length.It may seperate several times in the from to. I would like for the tool to adjust the length at the connect point. Any ideas? Thanks
Answer : In order to meet the phase tolerance, SPECCTRA is tuning the length of the shorter of the 2 nets by putting in 搕op hats? This however will sacrifice some of your acceptable uncoupled length in the process.
If you find that the amount of tuning is breaking away from your gathered etch more than you would like, try increasing your acceptable phase tolerance before autorouting to cut down on what SPECCTRA will automatically tune. Then, back in Allegro, you can reset the phase tolerance to what you can accept and use interactive controls to put in the extra length exactly where you want. This should be an easy task with the 揾eads up?meter assisting you.


4. How to create a detailed report?
Question: I want to create a detailed length report of whole board routing including vias. For example, a net starting from Connector pin goes to a resistor and finally terminating at deviceA. Actual flow is something like this:
(阅读次数:




相关报道:

信息搜索
PCB视频教程

PCB资源网 © 2007 | 服务热线:020-89811835 | QQ:28963805 | 电子邮件:联系PCB资源网