SPECCTRAQuest Floorplanner
Diff Pairs
A major focus of this release was to extend differential pair support across the entire product line. In Release 14.2, you could extract, explore, and simulate diff pair circuits in the SPECCTRAQuest environment. In Release 15.0, Constraint Manager supports the high-speed diff pair flow by letting you capture diff pair constraints, analyze diff pair circuits, and promote design intent directly to the layout.
Related simulation changes include the ability to apply a differential custom stimulus at the board level and support for differential buffer delays including the ability to assign an ESpice model as a test fixture in their computations. SigXplorer captures differential custom measurements and differential stimuli in a topology file which can then be promoted to Constraint Manager and applied to the design as an ECSet.
For more information, read Best Practices: Working With Differential Pairs.
DesignLink Creation
Enhancements to the System Configuration Editor make it easier to create DesignLinks. In addition to the manual method of typing in data when creating the PinMap, you can now choose from intelligent pull-down fields. These fields come seeded with design, component and pin number information based on your selections and the designs that comprise the system.
Additionally, when given two board names and a refdes, the new connect-by-component function can create a PinMap automatically. You can also select the source design for controlling system Xnet names.
Stack-up Editor Enhancements
With enhancements to its appearance, behavior, and performance, SPECCTRAQuest's stack-up editor now includes:
• An additional materials column, with the ability to classify semiconductor materials as a dielectric
• Dielectric and loss tangent values displayed now reflect data assigned in the materials.dat file and reflect the material selected
• The ability to define material, dielectric constant, and loss tangent for stripline layers
SPECCTRAQuest Power Integrity
Significant enhancements to SPECCTRAQuest Power Integrity include the following:
• You can now generate an HSpice version of a plane model used in multi-node simulation. The multimode.hspice file is saved in the run directory. This file contains many parameters used to characterize the planes.
• Multi-node simulations now include dielectric loss parameters. In multi-mode simulation mode, Power Integrity now computes values for fd (measurement frequency) and
g (dielectric shunt conductance).
• Filter improvements to the device set-up wizard let you quickly locate and select decoupling capacitors among all devices in the board database.
• Power Integrity lets you specify the rotation, and the side of the board, in which to place decoupling capacitors. Subsequent capacitor placement adheres to your preferences.
• Power Integrity computes mounted inductance for each instance of a capacitor on the board -- It is no longer a model property. You can choose to compute mounted inductance on placement or during MultiNode simulation, for all devices or only those without values. To save time, the same values can be used in different routing configurations.
• You can now define target impedance as a slope beyond a specified cut-off frequency.
• You can place the noise source anywhere on a component and it will follow the component if you move it. You can now edit the subcircuit as well.
Model Integrity
In its initial release, Model Integrity provided a good creation, manipulation, and validation environment for IBIS models. This functionality has been extended to DML models, allowing you access to the structure within a DML file. You can also use the marker navigation technology while debugging syntax errors in DML models.
HSPICE-to-IBIS
Many IC companies develop and distribute IO buffer models as encrypted HSPICE models. Although you can run these HSPICE models using the HSPICE engine, Model Integrity's new HSPICE-to-IBIS conversion module lets you create IBIS models from SPICE output (.lis) files.
Proven curve fitting and data extraction algorithms, used in the HSPICE to IBIS model creation process, were developed in partnership with a leading semiconductor manufacturer who has generated hundreds of IBIS models over the last 10 years. These algorithms provide the following functionality:
• Identification of SPICE I-V and V-t tables for Typ, Min, and Max corners.
• Recognition of buffer type, based on table data.
• Best points table reduction.
• Clamp current subtraction.
• On-die termination resistor identification.
• Model scaling to create corner models.
IBIS Syntax Parser
You can now specify any version of the ibischk3 parser. This affords you the flexibility of upreving from the 3.2 version as the IBIS committee releases updates to the Version 3 parser.
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